ROOE=0, CLR_TXF=0, HALT=0, MTFE=0, PCSIS=0, PCSSE=0, CLR_RXF=0, MDIS=0, SMPL_PT=00, MSTR=0, DOZE=0, DCONF=00, DIS_TXF=0, FRZ=0, DIS_RXF=0, CONT_SCKE=0
DSPI Module Configuration Register
| HALT | Halt 0 (0): Start transfers. 1 (1): Stop transfers. |
| SMPL_PT | Sample Point 0 (00): 0 system clocks between SCK edge and SIN sample 1 (01): 1 system clock between SCK edge and SIN sample 2 (10): 2 system clocks between SCK edge and SIN sample |
| CLR_RXF | no description available 0 (0): Do not clear the Rx FIFO counter. 1 (1): Clear the Rx FIFO counter. |
| CLR_TXF | Clear TX FIFO 0 (0): Do not clear the Tx FIFO counter. 1 (1): Clear the Tx FIFO counter. |
| DIS_RXF | Disable Receive FIFO 0 (0): Rx FIFO is enabled. 1 (1): Rx FIFO is disabled. |
| DIS_TXF | Disable Transmit FIFO 0 (0): Tx FIFO is enabled. 1 (1): Tx FIFO is disabled. |
| MDIS | Module Disable 0 (0): Enable DSPI clocks. 1 (1): Allow external logic to disable DSPI clocks. |
| DOZE | Doze Enable 0 (0): Doze mode has no effect on DSPI. 1 (1): Doze mode disables DSPI. |
| PCSIS | Peripheral Chip Select x Inactive State 0 (0): The inactive state of PCSx is low. 1 (1): The inactive state of PCSx is high. |
| ROOE | Receive FIFO Overflow Overwrite Enable 0 (0): Incoming data is ignored. 1 (1): Incoming data is shifted into the shift register. |
| PCSSE | Peripheral Chip Select Strobe Enable 0 (0): PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. 1 (1): PCS[5]/PCSS is used as an active-low PCS Strobe signal. |
| MTFE | Modified Timing Format Enable 0 (0): Modified SPI transfer format disabled. 1 (1): Modified SPI transfer format enabled. |
| FRZ | Freeze 0 (0): Do not halt serial transfers in debug mode. 1 (1): Halt serial transfers in debug mode. |
| DCONF | DSPI Configuration 0 (00): SPI |
| CONT_SCKE | Continuous SCK Enable 0 (0): Continuous SCK disabled. 1 (1): Continuous SCK enabled. |
| MSTR | Master/Slave Mode Select 0 (0): DSPI is in slave mode. 1 (1): DSPI is in master mode. |